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clock buffer/drive r w40s11-23 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 april 6, 2001 1w40s11-23 features ? thirteen skew-controlled cmos clock outputs (sdram0:12) supports three sdram dimms ideal for high-performance systems designed around intel?s latest chip set smbus serial configuration interface clock skew between any two outputs is less than 250 ps 1- to 5-ns propagation delay dc to 133-mhz operation single 3.3v supply voltage low power cmos design packaged in a 28-pin, 300-mil soic (small outline integrated circuit), 28-pin, 173-mil (thin shrink small outline package), and 28-pin, 209-mil ssop (small shrink outline package) overview the cypress w40s11-23 is a low-voltage, thirteen-output clock buffer. output buffer impedance is approximately 15 ? , which is ideal for driving sdram dimms. key specifications supply voltages:........................................... v dd = 3.3v5% operating temperature:.................................... 0c to +70c input threshold: .................................................. 1.5v typical maximum input voltage: .......................................v dd + 0.5v input frequency:............................................... 0 to 133 mhz buf_in to sdram0:12 propagation delay: ......1.0 to 5.0 ns output edge rate:.............................................. > 1.5 v/ns output clock skew: .................................................. 250 ps output duty cycle: .................................. 45/55% worst case output impedance:...............................................15 ? typical output type: ................................................ cmos rail-to-rail pin configuration soic block diagram note: 1. internal pull-up resistor of 250k on sdata and sclock inputs (not cmos level). [1] [1] sdram1 sdram2 sdram3 sdram4 sdram5 sdram6 sdram7 sdram8 sdram9 sdram10 sdram11 sdram12 sdram0 serial port sclock sdata device control buf_in vdd sdram0 sdram1 gnd vdd sdram2 sdram3 gnd buf_in sdram4 sdram5 sdram12 vdd sdata vdd sdram11 sdram10 gnd vdd sdram9 sdram8 gnd vdd sdram7 sdram6 gnd gnd sclock 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 [+] feedback
w40s11-23 2 functional description output drivers the w40s11-23 output buffers are cmos type which deliver a rail-to-rail (gnd to v dd ) output voltage swing into a nominal capacitive load. thus output signaling is both ttl and cmos level compatible. nominal output buffer impedance is 15 ? . operation data is written to the w40s11-23 in ten bytes of eight bits each. bytes are written in the order shown in ta b l e 1 . pin definitions pin name pin no. pin type pin description sdram0:12 2, 3, 6, 7, 10, 11, 18, 19, 22, 23, 26, 27, 12 o sdram outputs: provides buffered copy of buf_in. the propagation delay from a rising input edge to a rising output edge is 1 to 5 ns. all outputs are skew controlled to within 250 ps of each other. buf_in 9 i clock input: this clock input has an input threshold voltage of 1.5v (typ). sdata 14 i/o smbus data input: data should be presented to this input as described in the smbus section of this data sheet. internal 250-k ? pull-up resistor. sclock 15 i smbus clock input: the smbus data clock should be presented to this input as described in the smbus section of this data sheet. internal 250-k ? pull-up resistor. vdd 1, 5, 13, 20, 24, 28 p power connection: power supply for core logic and output buffers. connected to 3.3v supply. gnd 4, 8, 16, 17, 21, 25 g ground connection: connect all ground pins to the common system ground plane. table 1. byte writing sequence byte sequence byte name bit sequence byte description 1 slave address 11010010 commands the w40s11-23 to accept the bits in data bytes 0?6 for in- ternal register configuration. since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for each potential receiver. the slave receiver address for the w40s11-23 is 11010010. register setting will not be made if the slave address is not correct (or is for an alternate slave receiver). 2 command code don?t care unused by the w40s11-23, bit values are ignored (don?t care). this byte must be included in the data write sequence to maintain proper byte allocation. the command code byte is part of the standard serial com- munication protocol and may be used when writing to another addressed slave receiver on the serial data bus. 3 byte count don?t care unused by the w40s11-23, bit values are ignored (don?t care). this byte must be included in the data write sequence to maintain proper byte allocation. the byte count byte is part of the standard serial communi- cation protocol and may be used when writing to another addressed slave receiver on the serial data bus. 4 data byte 0 refer to ta b l e 2 the data bits in these bytes set internal w40s11-23 registers that control device operation. the data bits are only accepted when the address byte bit sequence is 11010010, as noted above. for description of bit control functions refer to ta b l e 2 . 5 data byte 1 6 data byte 2 7 data byte 3 don?t care refer to cypress frequency timing generators. 8 data byte 4 9 data byte 5 10 data byte 6 [+] feedback
w40s11-23 3 writing data bytes each bit in the data bytes control a particular device function. bits are written msb (most significant bit) first, which is bit 7. ta b l e 2 gives the bit formats for registers located in data bytes 0?6. note: 2. at power-up all sdram outputs are enabled and active. program reserved bits to a ?0.? table 2. data bytes 0?2 serial configuration map [2] bit(s) affected pin control function bit control pin no. pin name 0 1 data byte 0 sdram active/inactive register (1 = enable, 0 = disable) 7 11 sdram5 clock output disable low active 6 10 sdram4 clock output disable low active 5 n/a reserved (reserved) - - 4 n/a reserved (reserved) - - 3 7 sdram3 clock output disable low active 2 6 sdram2 clock output disable low active 1 3 sdram1 clock output disable low active 0 2 sdram0 clock output disable low active data byte 1 sdram active/inactive register (1 = enable, 0 = disable) 7 27 sdram11 clock output disable low active 6 26 sdram10 clock output disable low active 5 23 sdram9 clock output disable low active 4 22 sdram8 clock output disable low active 3 n/a reserved (reserved) - - 2 n/a reserved (reserved) - - 1 19 sdram7 clock output disable low active 0 18 sdram6 clock output disable low active data byte 2 sdram active/inactive register (1 = enable, 0 = disable) 7 n/a reserved (reserved) - - 6 12 sdram12 clock output disable low active 5 n/a reserved (reserved) -- -- 4 n/a reserved (reserved) -- -- 3 n/a reserved (reserved) -- -- 2 n/a reserved (reserved) -- -- 1 n/a reserved (reserved) -- -- 0 n/a reserved (reserved) -- -- [+] feedback
w40s11-23 4 how to use the serial data interface electrical requirements figure 1 illustrates electrical characteristics for the serial inter- face bus used with the w40s11-23. devices send data over the bus with an open drain logic output that can (a) pull the bus line low, or (b) let the bus default to logic 1. the pull-up resis- tor on the bus (both clock and data lines) establish a default logic 1. all bus devices generally have logic inputs to receive data. although the w40s11-23 is a receive-only device (no data write-back capability), it does transmit an ?acknowledge? data pulse after each byte is received. thus, the sdata line can both transmit and receive data. the pull-up resistor should be sized to meet the rise and fall times specified in ac parameters, taking into consideration to- tal bus line capacitance. data in data out n clock in clock out chip set (serial bus master transmitter) sdclk sdata serial bus clock line serial bus data line n data in data out clock in clock device (serial bus slave receiver) sclock sdata n ~ 2k ? ? ? ? ~ 2k ? ? ? ? vdd vdd figure 1. serial interface bus electrical characteristics [+] feedback
w40s11-23 5 signaling requirements as shown in figure 2 , valid data bits are defined as stable logic 0 or 1 condition on the data line during a clock high (logic 1) pulse. a transitioning data line during a clock high pulse may be interpreted as a start or stop pulse (it will be interpreted as a start or stop pulse if the start/stop timing parameters are met). a write sequence is initiated by a ?start bit? as shown in figure 3 . a ?stop bit? signifies that a transmission has ended. as stated previously, the w40s11-23 sends an ?acknowledge? pulse after receiving eight data bits in each byte as shown in figure 4 . sdata sclock valid data bit change of data allowed figure 2. serial data bus valid data bit sdata sclock start bit stop bit figure 3. serial data bus start and stop bit [+] feedback
w40s11-23 6 msb 12345678a12345678a 1234 sclock 12345678a 11 01 001 0 lsb msb msb lsb sdata sdata signaling from system core logic start condition msb lsb slave address (first byte) command code (second byte) last data byte (last byte) byte count (third byte) stop condition signaling by clock device acknowledgment bit from clock device figure 4. serial data bus write sequence t sthd t low t r t high t f t dsu t dhd t sp t spsu t sthd t spsu t spf sdata sclock figure 5. serial data bus timing diagram [+] feedback
w40s11-23 7 absolute maximum ratings stresses greater than those listed in this table may cause per- manent damage to the device. these represent a stress rating only. operation of the device at these or any other conditions above those specified in the operating sections of this specifi- cation is not implied. maximum conditions for extended peri- ods may affect reliability. parameter description rating unit v dd , v in voltage on any pin with respect to gnd ?0.5 to +7.0 v t stg storage temperature ?65 to +150 c t a operating temperature 0 to +70 c t b ambient temperature under bias ?55 to +125 c dc electrical characteristics: t a = 0c to +70c, v dd = 3.3v5% parameter description test condition/comments min. typ. max. unit i dd 3.3v supply current buf_in = 100 mhz 250 ma logic inputs v il input low voltage gnd?0.3 0.8 v v ih input high voltage 2.0 v dd +0.5 v i ileak input leakage current, buf_in ?5 +5 a i ileak input leakage current [3] ?20 +5 a logic outputs (sdram0:12) v ol output low voltage i ol = 1 ma 50 mv v oh output high voltage i oh = ?1 ma 3.1 v i ol output low current v ol = 1.5v 65 100 160 ma i oh output high current v oh = 1.5v 70 110 185 ma pin capacitance/inductance c in input pin capacitance 5pf c out output pin capacitance 6 pf l in input pin inductance 7nh note: 3. sdata and sclock logic pins have 250-k ? internal pull-up resistors. [+] feedback
w40s11-23 8 document #: 38-00793-*b ac electrical characteristics: t a = 0c to +70c, v dd = 3.3v 5% (lump capacitance test load = 30 pf) parameter description test condition min typ max unit f in input frequency 0 133 mhz t r output rise edge rate measured from 0.4v to 2.4v 1.5 4.0 v/ns t f output fall edge rate measured from 2.4v to 0.4v 1.5 4.0 v/ns t sr output skew, rising edges 250 ps t sf output skew, falling edges 250 ps t en output enable time 1.0 8.0 ns t dis output disable time 1.0 8.0 ns t pr rising edge propagation delay 1.0 5.0 ns t pf falling edge propagation delay 1.0 5.0 ns t d duty cycle measured at 1.5v 45 55 % z o ac output impedance 15 ? t pr rising edge propagation delay 1.0 5.0 ns ordering information ordering code freq. mask code package name package type w40s11 -23 g x h 28-pin soic (300 mils) 28-pin tssop (173 mil) 28-pin ssop (209 mil) [+] feedback
w40s11-23 9 package diagrams 28-pin small outline integrated circuit (soic, 0.300 inch) [+] feedback
w40s11-23 10 package diagrams (continued) 28-pin thin shrink small outline package (tssop, 173-mil) [+] feedback
w40s11-23 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package diagrams (continued) 28-pin small shrink outline package (ssop, 209 mils) [+] feedback

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